Micron Rules Out 4F² DRAM, Betting on Continued 6F² Scaling and Eventually 3D Memory

Micron has decided not to pursue DRAM built on 4F² memory cells, an architecture long viewed as a major prize in the memory industry. The company said that after working on the design for around twenty years, it found no meaningful density advantage, higher manufacturing complexity and cost, and fundamental limits on how far it can scale.

The 4F² label describes a cell whose area equals four times the square of the minimum lithographic feature size, versus six times for conventional 6F² DRAM. At the same feature size, that makes the cell about 33% smaller and could in theory raise the number of cells per wafer by 50%, cutting cost per bit. Realizing the gain, however, requires a suitable transistor design and a very compact capacitor arrangement, which is hard to achieve.

Scott DeBoer, Micron's president and chief technology and products officer, laid out the company's position at an event on Wednesday. "Micron invented 4F² DRAM," he said, adding that the company evaluated it repeatedly over the past two decades and chose not to pursue it because of the added complexity and cost.

His central argument is that capacitors, not transistors, set DRAM density. Capacitor pitch and size determine how many cells fit on a wafer, and both 4F² and 6F² transistor structures must sit beneath the capacitors. Shrinking the transistor alone therefore does not shrink the overall cell proportionally. "It is a bit of a myth that 4F² actually provides anything versus 6F²," DeBoer said, calling some of the comparison "smoke and mirrors."

The decision sets Micron apart from its rivals. According to TechInsights, Samsung and SK hynix both still list 4F² cells on their roadmaps. It is not the first time Micron has diverged: several years ago it held off on bringing EUV lithography into its manufacturing flow, unlike competitors, yet stayed competitive on cost and performance.

Instead, Micron intends to keep scaling 6F² DRAM by reducing capacitor pitch and shrinking process nodes. It expects advanced lithography, new materials and wafer bonding to extend planar DRAM scaling for several more generations. Its upcoming 1δ process, due in volume production in the second half of 2027, is expected to deliver a mid-20% gain in bit density over its predecessor, and the company plans to use High-NA EUV in future generations.

DeBoer acknowledged that 4F² is technically feasible and that Micron has built experimental devices using it. "4F² can be built back a few nodes, no question about it," he said, but it is more complex and costly, and beyond today's nodes "it is physics." He said the fundamental scaling problems will ultimately lead to 3D DRAM taking over instead. He did not name specific physical limits.

Micron's preferred long-term path is 3D DRAM, which stacks cells vertically rather than relying only on smaller lateral dimensions. The company is developing several generations of 3D DRAM nodes alongside its planar work, but has not said when the technology will reach commercial production. DeBoer indicated the move will come once 3D DRAM offers the right balance of density, manufacturing complexity and cost.

The stance contrasts with China-based CXMT, which recently praised 4F². Micron's argument that a company can either adopt 4F² or use more sophisticated process technologies may help explain that divergence.